Cypress Semiconductor /psoc63 /CPUSS /CM0_CLOCK_CTL

Specifies the slow clock divider (from the peripheral clock ‘clk_peri’ to the slow clock ‘clk_slow’). Integer division by (1+SLOW_INT_DIV). Allows for integer divisions in the range [1, 256] (SLOW_INT_DIV is in the range [0, 255]).

Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to ‘0’ when transitioning from DeepSleep to Active power mode.

Specifies the peripheral clock divider (from the high frequency clock ‘clk_hf’ to the peripheral clock ‘clk_peri’). Integer division by (1+PERI_INT_DIV). Allows for integer divisions in the range [1, 256] (PERI_INT_DIV is in the range [0, 255]).

Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to ‘0’ when transitioning from DeepSleep to Active power mode.

Note that Fperi <= Fperi_max. Fperi_max is likely to be smaller than Fhf_max. In other words, if Fhf = Fhf_max, PERI_INT_DIV should not be set to ‘0’.